AND Gate
INPUT | OUTPUT | |
---|---|---|
A | B | |
0 | 0 | 0 |
1 | 0 | 0 |
0 | 1 | 0 |
1 | 1 | 1 |
OR Gate
INPUT | OUTPUT | |
---|---|---|
A | B | |
0 | 0 | 0 |
1 | 0 | 1 |
0 | 1 | 1 |
1 | 1 | 1 |
NOT Gate
INPUT | OUTPUT |
---|---|
A | |
0 | 1 |
1 | 0 |
XOR Gate
INPUT | OUTPUT | |
---|---|---|
A | B | |
0 | 0 | 0 |
1 | 0 | 1 |
0 | 1 | 1 |
1 | 1 | 0 |
INPUT | OUTPUT | |
---|---|---|
A | B | |
0 | 0 | 0 |
1 | 0 | 0 |
0 | 1 | 0 |
1 | 1 | 1 |
INPUT | OUTPUT | |
---|---|---|
A | B | |
0 | 0 | 0 |
1 | 0 | 1 |
0 | 1 | 1 |
1 | 1 | 1 |
INPUT | OUTPUT |
---|---|
A | |
0 | 1 |
1 | 0 |
INPUT | OUTPUT | |
---|---|---|
A | B | |
0 | 0 | 0 |
1 | 0 | 1 |
0 | 1 | 1 |
1 | 1 | 0 |